Consider a 5-stage pipelined architecture similar to the one discussed in class. The 5 stages are fetch (IF), decode (ID), execute (EX), memory (MEM), and write back (WB). The processor executes a program with 10 instructions. The instructions do not have any data dependencies, hazards, or bubbles/stalls. The below table mentions the latency of each stage.
IF | ID | EX | MEM | WB
Execution Time (ns) 2 1.5 2.5 4 1
(a) What is the least possible cycle time of this processor?
